Makefile ARM C Template
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#########################################################################
# #
# Template Makefile for C Programs #
# #
#########################################################################
# This file is meant to be used as a template (in other words, a starting
# point) for any Makefile that you write. Modify it to suit your needs,
# making sure that the file is called "Makefile"; in most cases, all you
# need to do is replace every occurrence of "template" with the name of
# your file.
#
# Every Makefile should have the targets "all" and "clean", at a minimum.
# See chapter 14 of the GNU Make Reference for other suggestions on how
# Makefiles should be written.
#
# Please note that every line that is indented (or, in the language of
# Makefiles, the command part of the rules) is done so with TAB
# characters, NOT with spaces. This is important and a subtle trap for
# the unwary!
all: template.elf
template.elf: template.o
template.o: template.c template.h
clean:
-rm -f template.elf template.o
# The following variables and implicit rules are required for the GNU
# Assembler and the GNU Compiler for ARM. You probably do not need to
# modify anything here.
AS = arm-none-eabi-as
CC = arm-none-eabi-gcc
LD = arm-none-eabi-ld
ASFLAGS = --gdwarf2
CFLAGS = -O2 -g -Wall
LDFLAGS =
LOADLIBES =
LDLIBS = -lc
# Compile C code (.c) to an object file (.o)
%.o: %.c
$(CC) -c -mcpu=arm7tdmi $(CFLAGS) $< -o $@
# Assemble ARM assembly language source (.s) to an object file (.o)
%.o: %.s
$(AS) -marm7tdmi $(ASFLAGS) $< -o $@
# Link files into an ARM executable (.elf), using the GNU Compiler.
%.elf:
$(CC) $(LDFLAGS) $+ $(LOADLIBES) $(LDLIBS) -o $@
# Miscellaneous rules
.PHONY: all clean
.DEFAULT:
.SUFFIXES:
Reference