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EmSys

Tm4clib-nvic-defines

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Cortex M0/M3/M4 System Interrupts

IRQ numbers -3 and -6 to -9 are reserved.

Macro Definition

NVIC_ICER

/* ICER: Interrupt Clear Enable Registers */
#define NVIC_ICER(icer_id)
Value:

MMIO32(NVIC_BASE + 0x80 + ((icer_id) * 4))

NVIC_ICPR

/* ICPR: Interrupt Clear Pending Registers */
#define NVIC_ICPR(icpr_id)
Value:

MMIO32(NVIC_BASE + 0x180 + ((icpr_id) * 4))

NVIC_IPR

/* IPR: Interrupt Priority Registers */
#define NVIC_IPR(ipr_id)
Value:

MMIO8(NVIC_BASE + 0x300 + (ipr_id))

NVIC_ISER

/* ISER: Interrupt Set Enable Registers */
#define NVIC_ISER(iser_id)
Value:

MMIO32(NVIC_BASE + 0x00 + ((iser_id) * 4))

NVIC_ISPR

/* ISPR: Interrupt Set Pending Registers */
#define NVIC_ISPR(ispr_id)
Value:

MMIO32(NVIC_BASE + 0x100 + ((ispr_id) * 4))

NVIC_HARD_FAULT_IRQ

#define NVIC_HARD_FAULT_IRQ -13

NVIC_NMI_IRQ

#define NVIC_NMI_IRQ -14

NVIC_PENDSV_IRQ

#define NVIC_PENDSV_IRQ -2

NVIC_SV_CALL_IRQ

#define NVIC_SV_CALL_IRQ -5

NVIC_SYSTICK_IRQ

#define NVIC_SYSTICK_IRQ -1

User interrupts for TIVA C series

NVIC_GPIOA_IRQ

#define NVIC_GPIOA_IRQ 0

NVIC_GPIOB_IRQ

#define NVIC_GPIOB_IRQ 1

NVIC_GPIOC_IRQ

#define NVIC_GPIOC_IRQ 2

NVIC_GPIOD_IRQ

#define NVIC_GPIOD_IRQ 3

NVIC_GPIOE_IRQ

#define NVIC_GPIOE_IRQ 4

NVIC_UART0_IRQ

#define NVIC_UART0_IRQ 5

NVIC_UART1_IRQ

#define NVIC_UART1_IRQ 6

NVIC_SSI0_IRQ

#define NVIC_SSI0_IRQ 7

NVIC_I2C0_IRQ

#define NVIC_I2C0_IRQ 8

NVIC_PWM0_FAULT_IRQ

#define NVIC_PWM0_FAULT_IRQ 9

NVIC_PWM0_0_IRQ

#define NVIC_PWM0_0_IRQ 10

NVIC_PWM0_1_IRQ

#define NVIC_PWM0_1_IRQ 11

NVIC_PWM0_2_IRQ

#define NVIC_PWM0_2_IRQ 12

NVIC_QEI0_IRQ

#define NVIC_QEI0_IRQ 13

NVIC_ADC0SS0_IRQ

#define NVIC_ADC0SS0_IRQ 14

NVIC_ADC0SS1_IRQ

#define NVIC_ADC0SS1_IRQ 15

NVIC_ADC0SS2_IRQ

#define NVIC_ADC0SS2_IRQ 16

NVIC_ADC0SS3_IRQ

#define NVIC_ADC0SS3_IRQ 17

NVIC_WATCHDOG_IRQ

#define NVIC_WATCHDOG_IRQ 18

NVIC_TIMER0A_IRQ

#define NVIC_TIMER0A_IRQ 19

NVIC_TIMER0B_IRQ

#define NVIC_TIMER0B_IRQ 20

NVIC_TIMER1A_IRQ

#define NVIC_TIMER1A_IRQ 21

NVIC_TIMER1B_IRQ

#define NVIC_TIMER1B_IRQ 22

NVIC_TIMER2A_IRQ

#define NVIC_TIMER2A_IRQ 23

NVIC_TIMER2B_IRQ

#define NVIC_TIMER2B_IRQ 24

NVIC_COMP0_IRQ

#define NVIC_COMP0_IRQ 25

NVIC_COMP1_IRQ

#define NVIC_COMP1_IRQ 26

NVIC_COMP2_IRQ

#define NVIC_COMP2_IRQ 27

NVIC_SYSCTL_IRQ

#define NVIC_SYSCTL_IRQ 28

NVIC_FLASH_IRQ

#define NVIC_FLASH_IRQ 29

NVIC_GPIOF_IRQ

#define NVIC_GPIOF_IRQ 30

NVIC_GPIOG_IRQ

#define NVIC_GPIOG_IRQ 31

NVIC_GPIOH_IRQ

#define NVIC_GPIOH_IRQ 32

NVIC_UART2_IRQ

#define NVIC_UART2_IRQ 33

NVIC_SSI1_IRQ

#define NVIC_SSI1_IRQ 34

NVIC_TIMER3A_IRQ

#define NVIC_TIMER3A_IRQ 35

NVIC_TIMER3B_IRQ

#define NVIC_TIMER3B_IRQ 36

NVIC_I2C1_IRQ

#define NVIC_I2C1_IRQ 37

NVIC_QEI1_IRQ

#define NVIC_QEI1_IRQ 38

NVIC_CAN0_IRQ

#define NVIC_CAN0_IRQ 39

NVIC_CAN1_IRQ

#define NVIC_CAN1_IRQ 40

NVIC_CAN2_IRQ

#define NVIC_CAN2_IRQ 41

NVIC_ETH_IRQ

#define NVIC_ETH_IRQ 42

NVIC_HIBERNATE_IRQ

#define NVIC_HIBERNATE_IRQ 43

NVIC_USB0_IRQ

#define NVIC_USB0_IRQ 44

NVIC_PWM0_3_IRQ

#define NVIC_PWM0_3_IRQ 45

NVIC_UDMA_IRQ

#define NVIC_UDMA_IRQ 46

NVIC_UDMAERR_IRQ

#define NVIC_UDMAERR_IRQ 47

NVIC_ADC1SS0_IRQ

#define NVIC_ADC1SS0_IRQ 48

NVIC_ADC1SS1_IRQ

#define NVIC_ADC1SS1_IRQ 49

NVIC_ADC1SS2_IRQ

#define NVIC_ADC1SS2_IRQ 50

NVIC_ADC1SS3_IRQ

#define NVIC_ADC1SS3_IRQ 51

NVIC_I2S0_IRQ

#define NVIC_I2S0_IRQ 52

NVIC_EPI0_IRQ

#define NVIC_EPI0_IRQ 53

NVIC_GPIOJ_IRQ

#define NVIC_GPIOJ_IRQ 54

NVIC_GPIOK_IRQ

#define NVIC_GPIOK_IRQ 55

NVIC_GPIOL_IRQ

#define NVIC_GPIOL_IRQ 56

NVIC_SSI2_IRQ

#define NVIC_SSI2_IRQ 57

NVIC_SSI3_IRQ

#define NVIC_SSI3_IRQ 58

NVIC_UART3_IRQ

#define NVIC_UART3_IRQ 59

NVIC_UART4_IRQ

#define NVIC_UART4_IRQ 60

NVIC_UART5_IRQ

#define NVIC_UART5_IRQ 61

NVIC_UART6_IRQ

#define NVIC_UART6_IRQ 62

NVIC_UART7_IRQ

#define NVIC_UART7_IRQ 63

NVIC_I2C2_IRQ

#define NVIC_I2C2_IRQ 68

NVIC_I2C3_IRQ

#define NVIC_I2C3_IRQ 69

NVIC_TIMER4A_IRQ

#define NVIC_TIMER4A_IRQ 70

NVIC_TIMER4B_IRQ

#define NVIC_TIMER4B_IRQ 71

NVIC_TIMER5A_IRQ

#define NVIC_TIMER5A_IRQ 92

NVIC_TIMER5B_IRQ

#define NVIC_TIMER5B_IRQ 93

NVIC_WTIMER0A_IRQ

#define NVIC_WTIMER0A_IRQ 94

NVIC_WTIMER0B_IRQ

#define NVIC_WTIMER0B_IRQ 95

NVIC_WTIMER1A_IRQ

#define NVIC_WTIMER1A_IRQ 96

NVIC_WTIMER1B_IRQ

#define NVIC_WTIMER1B_IRQ 97

NVIC_WTIMER2A_IRQ

#define NVIC_WTIMER2A_IRQ 98

NVIC_WTIMER2B_IRQ

#define NVIC_WTIMER2B_IRQ 99

NVIC_WTIMER3A_IRQ

#define NVIC_WTIMER3A_IRQ 100

NVIC_WTIMER3B_IRQ

#define NVIC_WTIMER3B_IRQ 101

NVIC_WTIMER4A_IRQ

#define NVIC_WTIMER4A_IRQ 102

NVIC_WTIMER4B_IRQ

#define NVIC_WTIMER4B_IRQ 103

NVIC_WTIMER5A_IRQ

#define NVIC_WTIMER5A_IRQ 104

NVIC_WTIMER5B_IRQ

#define NVIC_WTIMER5B_IRQ 105

NVIC_SYSEXC_IRQ

#define NVIC_SYSEXC_IRQ 106

NVIC_PECI0_IRQ

#define NVIC_PECI0_IRQ 107

NVIC_LPC0_IRQ

#define NVIC_LPC0_IRQ 108

NVIC_I2C4_IRQ

#define NVIC_I2C4_IRQ 109

NVIC_I2C5_IRQ

#define NVIC_I2C5_IRQ 110

NVIC_GPIOM_IRQ

#define NVIC_GPIOM_IRQ 111

NVIC_GPION_IRQ

#define NVIC_GPION_IRQ 112

NVIC_FAN0_IRQ

#define NVIC_FAN0_IRQ 114

NVIC_GPIOP0_IRQ

#define NVIC_GPIOP0_IRQ 116

NVIC_GPIOP1_IRQ

#define NVIC_GPIOP1_IRQ 117

NVIC_GPIOP2_IRQ

#define NVIC_GPIOP2_IRQ 118

NVIC_GPIOP3_IRQ

#define NVIC_GPIOP3_IRQ 119

NVIC_GPIOP4_IRQ

#define NVIC_GPIOP4_IRQ 120

NVIC_GPIOP5_IRQ

#define NVIC_GPIOP5_IRQ 121

NVIC_GPIOP6_IRQ

#define NVIC_GPIOP6_IRQ 122

NVIC_GPIOP7_IRQ

#define NVIC_GPIOP7_IRQ 123

NVIC_GPIOQ0_IRQ

#define NVIC_GPIOQ0_IRQ 124

NVIC_GPIOQ1_IRQ

#define NVIC_GPIOQ1_IRQ 125

NVIC_GPIOQ2_IRQ

#define NVIC_GPIOQ2_IRQ 126

NVIC_GPIOQ3_IRQ

#define NVIC_GPIOQ3_IRQ 127

NVIC_GPIOQ4_IRQ

#define NVIC_GPIOQ4_IRQ 128

NVIC_GPIOQ5_IRQ

#define NVIC_GPIOQ5_IRQ 129

NVIC_GPIOQ6_IRQ

#define NVIC_GPIOQ6_IRQ 130

NVIC_GPIOQ7_IRQ

#define NVIC_GPIOQ7_IRQ 131

NVIC_PWM1_0_IRQ

#define NVIC_PWM1_0_IRQ 134

NVIC_PWM1_1_IRQ

#define NVIC_PWM1_1_IRQ 135

NVIC_PWM1_2_IRQ

#define NVIC_PWM1_2_IRQ 136

NVIC_PWM1_3_IRQ

#define NVIC_PWM1_3_IRQ 137

NVIC_PWM1_FAULT_IRQ

#define NVIC_PWM1_FAULT_IRQ 138

NVIC_IRQ_COUNT

#define NVIC_IRQ_COUNT 139