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Tm4clib-scb-registers

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SCB Registers

Macros

#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
CPUID: CPUID base register. More...

#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
ICSR: Interrupt Control State Register. More...

#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
VTOR: Vector Table Offset Register. More...

#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
AIRCR: Application Interrupt and Reset Control Register. More...

#define SCB_SCR MMIO32(SCB_BASE + 0x10)
SCR: System Control Register. More...

#define SCB_CCR MMIO32(SCB_BASE + 0x14)
CCR: Configuration Control Register. More...

#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + (shpr_id))
SHP: System Handler Priority Registers. More...

#define SCB_SHPR1 MMIO32(SCB_BASE + 0x18)
#define SCB_SHPR2 MMIO32(SCB_BASE + 0x1C)
#define SCB_SHPR3 MMIO32(SCB_BASE + 0x20)
#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
SHCSR: System Handler Control and State Register. More...

#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
DFSR: Debug Fault Status Register. More...

Detailed Description

SCB_AIRCR

#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
AIRCR: Application Interrupt and Reset Control Register.

SCB_CCR

#define SCB_CCR MMIO32(SCB_BASE + 0x14)
CCR: Configuration Control Register.

SCB_CPUID

#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
CPUID: CPUID base register.

SCB_DFSR

#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
DFSR: Debug Fault Status Register.

SCB_ICSR

#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
ICSR: Interrupt Control State Register.

SCB_SCR

#define SCB_SCR MMIO32(SCB_BASE + 0x10)
SCR: System Control Register.

SCB_SHCSR

#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
SHCSR: System Handler Control and State Register.

SCB_SHPR

#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + (shpr_id))
SHP: System Handler Priority Registers.
Note: 12 8bit registers

SCB_SHPR1

#define SCB_SHPR1 MMIO32(SCB_BASE + 0x18)

SCB_SHPR2

#define SCB_SHPR2 MMIO32(SCB_BASE + 0x1C)

SCB_SHPR3

#define SCB_SHPR3 MMIO32(SCB_BASE + 0x20)

SCB_VTOR

#define SCB_VTOR MMIO32(SCB_BASE + 0x08) VTOR: Vector Table Offset Register.