Actions

EmSys

Difference between revisions of "TM4C123GXL GPIO - Setup the drive strength for each pin"

From EdWiki

(Created page with "__NOTOC__ == GPIO - Setup the drive strength for each pin == Optionally, you can setup the drive strength for each pin through the GPIODR2R, GPIODR4R, or GPIODR8R registers. T...")
 
m
Line 2: Line 2:
 
== GPIO - Setup the drive strength for each pin ==
 
== GPIO - Setup the drive strength for each pin ==
 
Optionally, you can setup the drive strength for each pin through the GPIODR2R, GPIODR4R, or GPIODR8R registers. This step is optional since the default drive strength is 2 mA.
 
Optionally, you can setup the drive strength for each pin through the GPIODR2R, GPIODR4R, or GPIODR8R registers. This step is optional since the default drive strength is 2 mA.
 +
 +
The pad control registers allow software to configure the GPIO pads based on the application requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength, open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable
 +
for each GPIO. If 5 V is applied to a GPIO configured as an open-drain output, the output voltage will depend on the strength of your pull-up resistor. The GPIO pad is not electrically configured to output 5 V.
 +
 +
=== GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ===
 +
The GPIODR2R register is the 2-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware. By default, all GPIO pins have 2-mA drive.
 +
 +
[[image:tm4c_gpiodr2r_r.png|center]]

Revision as of 07:01, 3 June 2019

GPIO - Setup the drive strength for each pin

Optionally, you can setup the drive strength for each pin through the GPIODR2R, GPIODR4R, or GPIODR8R registers. This step is optional since the default drive strength is 2 mA.

The pad control registers allow software to configure the GPIO pads based on the application requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength, open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable for each GPIO. If 5 V is applied to a GPIO configured as an open-drain output, the output voltage will depend on the strength of your pull-up resistor. The GPIO pad is not electrically configured to output 5 V.

GPIO 2-mA Drive Select (GPIODR2R), offset 0x500

The GPIODR2R register is the 2-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware. By default, all GPIO pins have 2-mA drive.

Tm4c gpiodr2r r.png