Difference between revisions of "TM4C123GXL PLL Sample Program"
From EdWiki
m (→PLL Source Code) |
m (→PLL Sample Program) |
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void PLL_Init(void) | void PLL_Init(void) | ||
{ | { | ||
| − | /* 1) configure the system to use RCC2 for advanced features | + | /* (1) configure the system to use RCC2 for advanced features |
such as 400 MHz PLL and non-integer System Clock Divisor */ | such as 400 MHz PLL and non-integer System Clock Divisor */ | ||
SYSCTL_RCC2_R |= SYSCTL_RCC2_USERCC2; | SYSCTL_RCC2_R |= SYSCTL_RCC2_USERCC2; | ||
| − | /* 2) bypass PLL while initializing */ | + | /* (2) bypass PLL while initializing */ |
SYSCTL_RCC2_R |= SYSCTL_RCC2_BYPASS2; | SYSCTL_RCC2_R |= SYSCTL_RCC2_BYPASS2; | ||
| − | /* 3) select the crystal value and oscillator source */ | + | /* (3) select the crystal value and oscillator source */ |
SYSCTL_RCC_R &= ~SYSCTL_RCC_XTAL_M; /* clear XTAL field */ | SYSCTL_RCC_R &= ~SYSCTL_RCC_XTAL_M; /* clear XTAL field */ | ||
SYSCTL_RCC_R += SYSCTL_RCC_XTAL_16MHZ; /* configure for 16 MHz crystal */ | SYSCTL_RCC_R += SYSCTL_RCC_XTAL_16MHZ; /* configure for 16 MHz crystal */ | ||
SYSCTL_RCC2_R &= ~SYSCTL_RCC2_OSCSRC2_M; /* clear oscillator source field */ | SYSCTL_RCC2_R &= ~SYSCTL_RCC2_OSCSRC2_M; /* clear oscillator source field */ | ||
SYSCTL_RCC2_R += SYSCTL_RCC2_OSCSRC2_MO; /* configure for main oscillator source */ | SYSCTL_RCC2_R += SYSCTL_RCC2_OSCSRC2_MO; /* configure for main oscillator source */ | ||
| − | /* 4) activate PLL by clearing PWRDN */ | + | /* (4) activate PLL by clearing PWRDN */ |
SYSCTL_RCC2_R &= ~SYSCTL_RCC2_PWRDN2; | SYSCTL_RCC2_R &= ~SYSCTL_RCC2_PWRDN2; | ||
| − | /* 5) set the desired system divider and the system divider least significant bit */ | + | /* (5) set the desired system divider and the system divider least significant bit */ |
SYSCTL_RCC2_R |= SYSCTL_RCC2_DIV400; /* use 400 MHz PLL */ | SYSCTL_RCC2_R |= SYSCTL_RCC2_DIV400; /* use 400 MHz PLL */ | ||
| − | + | /* clear system clock divider field and configure for 80 MHz clock */ | |
| − | + | SYSCTL_RCC2_R = (SYSCTL_RCC2_R&~0x1FC00000)+(Bus80MHz<<22); | |
| − | /* 6) wait for the PLL to lock by polling PLLLRIS */ | + | /* (6) wait for the PLL to lock by polling PLLLRIS */ |
while((SYSCTL_RIS_R&SYSCTL_RIS_PLLLRIS)==0){ | while((SYSCTL_RIS_R&SYSCTL_RIS_PLLLRIS)==0){ | ||
; | ; | ||
} | } | ||
| − | /* 7) enable use of PLL by clearing BYPASS */ | + | /* (7) enable use of PLL by clearing BYPASS */ |
SYSCTL_RCC2_R &= ~SYSCTL_RCC2_BYPASS2; | SYSCTL_RCC2_R &= ~SYSCTL_RCC2_BYPASS2; | ||
} | } | ||
</syntaxhighlight> | </syntaxhighlight> | ||
Latest revision as of 07:33, 15 March 2022
PLL Sample Program
/* Configure the system to get its clock from the PLL */#include <stdint.h>#include "inc/tm4c123gh6pm.h"#define SYSCTL_RIS_PLLLRIS 0x00000040 /* PLL Lock Raw Interrupt Status */#define SYSCTL_RCC_XTAL_M 0x000007C0 /* Crystal Value */#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 /* 6 MHz Crystal */#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 /* 8 MHz Crystal */#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 /* 16 MHz Crystal */#define SYSCTL_RCC2_USERCC2 0x80000000 /* Use RCC2 */#define SYSCTL_RCC2_DIV400 0x40000000 /* Divide PLL as 400 MHz vs. 200 MHz */#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 /* System Clock Divisor 2 */#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 /* Additional LSB for SYSDIV2 */#define SYSCTL_RCC2_PWRDN2 0x00002000 /* Power-Down PLL 2 */#define SYSCTL_RCC2_BYPASS2 0x00000800 /* PLL Bypass 2 */#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 /* Oscillator Source 2 */#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 /* MOSC */#define Bus80MHz 4void PLL_Init(void)
{/* (1) configure the system to use RCC2 for advanced featuressuch as 400 MHz PLL and non-integer System Clock Divisor */SYSCTL_RCC2_R |= SYSCTL_RCC2_USERCC2;
/* (2) bypass PLL while initializing */SYSCTL_RCC2_R |= SYSCTL_RCC2_BYPASS2;
/* (3) select the crystal value and oscillator source */SYSCTL_RCC_R &= ~SYSCTL_RCC_XTAL_M; /* clear XTAL field */
SYSCTL_RCC_R += SYSCTL_RCC_XTAL_16MHZ; /* configure for 16 MHz crystal */
SYSCTL_RCC2_R &= ~SYSCTL_RCC2_OSCSRC2_M; /* clear oscillator source field */
SYSCTL_RCC2_R += SYSCTL_RCC2_OSCSRC2_MO; /* configure for main oscillator source */
/* (4) activate PLL by clearing PWRDN */SYSCTL_RCC2_R &= ~SYSCTL_RCC2_PWRDN2;
/* (5) set the desired system divider and the system divider least significant bit */SYSCTL_RCC2_R |= SYSCTL_RCC2_DIV400; /* use 400 MHz PLL */
/* clear system clock divider field and configure for 80 MHz clock */SYSCTL_RCC2_R = (SYSCTL_RCC2_R&~0x1FC00000)+(Bus80MHz<<22);
/* (6) wait for the PLL to lock by polling PLLLRIS */while((SYSCTL_RIS_R&SYSCTL_RIS_PLLLRIS)==0){
;}/* (7) enable use of PLL by clearing BYPASS */SYSCTL_RCC2_R &= ~SYSCTL_RCC2_BYPASS2;
}