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Difference between revisions of "TM4C123 GPTM Interrupt Programming"

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IRQ21 is assigned to Timer1A and IRQ23 to Timer2A. The following will enable these timers in NVIC:
 
IRQ21 is assigned to Timer1A and IRQ23 to Timer2A. The following will enable these timers in NVIC:
  
  NVIC_ENG0_R |= 0x00200000;/* enable IRQ21  */
+
  NVIC_ENG0_R |= 0x00200000;   /* enable IRQ21  */
  NVIC_ENG0_R |= 0x00800000; /* enable IRQ23 */
+
  NVIC_ENG0_R |= 0x00800000;   /* enable IRQ23 */
  
 
'''Task 2''': '''Use Timer1A and Timer2A timeout events to trigger interrupts'''.
 
'''Task 2''': '''Use Timer1A and Timer2A timeout events to trigger interrupts'''.

Revision as of 06:31, 27 February 2018

Timer Interrupt Programming

In the previous article, we showed how to program the timers. In those programming examples, we used polling to see if a timeout event occurred. In this section, we give interrupt-based version of those programs. Examine the earlier programs, we could run those programs only one at a time since we have to monitor the timer flag continuously. By using interrupt, we can run several of timer programs all at the same. To do that, we need to enable the timer interrupts using the GPTMIMR (GPTM Interrupt Mask) register.

Tm4c gptm imr.png
Bit Name Description
0 TATOIM Timer A Time-out Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
1 CAMIM Timer A Capture Mode Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
2 CAEIM Timer A Capture Mode Event Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
3 RTCIM RTC Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
4 TAMIM Timer A Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
8 TBTOIM Timer B Time-out Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
9 CBMIM Timer B Capture Mode Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
10 CBEIM Timer B Capture Mode Event Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
11 TBMIM Timer B Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
16 WUEIM 32/64-Bit Wide GPTM Write Update Error Interrupt Mask (0:disabled, 1:enabled)
Table 10.1: GPTM Interrupt Mask (GPTMIMR)

IRQ21 is assigned to Timer1A and IRQ23 to Timer2A. The following will enable these timers in NVIC:

NVIC_ENG0_R |= 0x00200000;   /* enable IRQ21  */
NVIC_ENG0_R |= 0x00800000;   /* enable IRQ23 */

Task 2: Use Timer1A and Timer2A timeout events to trigger interrupts.

  • Configure Timer1A to timeout once every second. In the interrupt handler, toggle the red LED.
  • Configure Timer2A to timeout at 10 Hz. In the interrupt handler, toggle the green LED.
  • The infinite loop in the main program should blink the blue LED while the interrupts are going on.


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