Actions

EmSys

Difference between revisions of "TM4C123 GPTM Interrupt Programming"

From EdWiki

m (Timer Interrupt Programming)
m (Timer Interrupt Programming)
 
(22 intermediate revisions by the same user not shown)
Line 1: Line 1:
 +
__NOTOC__
 
== Timer Interrupt Programming ==
 
== Timer Interrupt Programming ==
 
In the previous article, we showed how to program the timers. In those programming examples, we used polling to see if a timeout event occurred. In this section, we give interrupt-based version of those programs. Examine the earlier programs, we could run those programs only one at a time since we have to monitor the timer flag continuously. By using interrupt, we can run several of timer programs all at the same. To do that, we need to enable the timer interrupts using the '''GPTMIMR''' (GPTM Interrupt Mask) register.
 
In the previous article, we showed how to program the timers. In those programming examples, we used polling to see if a timeout event occurred. In this section, we give interrupt-based version of those programs. Examine the earlier programs, we could run those programs only one at a time since we have to monitor the timer flag continuously. By using interrupt, we can run several of timer programs all at the same. To do that, we need to enable the timer interrupts using the '''GPTMIMR''' (GPTM Interrupt Mask) register.
 +
=== Timers A and B Interrupt and Configuration Register Group ===
 +
Six registers are used to control and handle interrupts of the Timers A and B:
 +
* GPTM Interrupt Mask Register (GPTMIMR)
 +
* GPTM Raw Interrupt Status Register (GPTMRIS)
 +
* GPTM Masked Interrupt Status Register (GPTMMIS)
 +
* GPTM Interrupt Clear Register (GPTMICR)
 +
* ''GPTM Synchronize Register (GPTMSYNC)''
 +
* ''GPTM Peripheral Properties Register (GPTMPP)''
 +
 +
==== GPTM Interrupt Mask Register (GPTMIMR) ====
  
 
[[image:tm4c_gptm_imr.png|center]]
 
[[image:tm4c_gptm_imr.png|center]]
 +
  
 
{| class="wikitable" style="margin: auto;"
 
{| class="wikitable" style="margin: auto;"
Line 8: Line 20:
 
! Bit !! Name !! Description
 
! Bit !! Name !! Description
 
|-
 
|-
| 0 || TATOIM || Timer A Time-out Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
+
| 0 || TATOIM || Timer A Time-out Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
 
|-
 
|-
| 1 || CAMIM || Timer A Capture Mode Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
+
| 1 || CAMIM || Timer A Capture Mode Match Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
 
|-
 
|-
| 2 || CAEIM || Timer A Capture Mode Event Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
+
| 2 || CAEIM || Timer A Capture Mode Event Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
 
|-
 
|-
| 3 || RTCIM || RTC Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
+
| 3 || RTCIM || RTC Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
 
|-
 
|-
| 4 || TAMIM || Timer A Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
+
| 4 || TAMIM || Timer A Match Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
 
|-
 
|-
| 8 || TBTOIM || Timer B Time-out Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
+
| 8 || TBTOIM || Timer B Time-out Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
 
|-
 
|-
| 9 || CBMIM || Timer B Capture Mode Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
+
| 9 || CBMIM || Timer B Capture Mode Match Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
 
|-
 
|-
| 10 || CBEIM || Timer B Capture Mode Event Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
+
| 10 || CBEIM || Timer B Capture Mode Event Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
 
|-
 
|-
| 11 || TBMIM || Timer B Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
+
| 11 || TBMIM || Timer B Match Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
 
|-
 
|-
| 16 || WUEIM || 32/64-Bit Wide GPTM Write Update Error Interrupt Mask (0:disabled, 1:enabled)
+
| 16 || WUEIM || 32/64-Bit Wide GPTM Write Update Error Interrupt Mask (0: disabled, 1: enabled)
 
|}
 
|}
 
<div style="text-align: center;">'''Table 10.1''': GPTM Interrupt Mask (GPTMIMR)</div>
 
<div style="text-align: center;">'''Table 10.1''': GPTM Interrupt Mask (GPTMIMR)</div>
 +
  
 
IRQ21 is assigned to Timer1A and IRQ23 to Timer2A. The following will enable these timers in NVIC:
 
IRQ21 is assigned to Timer1A and IRQ23 to Timer2A. The following will enable these timers in NVIC:
Line 35: Line 48:
 
  NVIC_EN0_R |= 0x00800000;  /* enable IRQ23 */
 
  NVIC_EN0_R |= 0x00800000;  /* enable IRQ23 */
  
'''Task 2''': '''Build a General Purpose Timer Project'''.
+
=== GPTM Raw Interrupt Status Register (GPTMRIS) ===
  
Use GPTM block 0 Timer A (Timer0A) as a 16-bit count-down counter to periodically generate a timeout interrupt to turn on three LEDs, PF3∼PF1, via GPIO Port F. The input clock to the timer is the 16 MHz system clock, and the period to be counted in the Timer0A counter is 65.536 ms.
+
[[image:tm4c_gptmris_r.png|center]]
 +
 
 +
 
 +
This 32-bit register only used the lower 10 bits to monitor and set a raw or internal interrupt if a GPTM-related raw interrupt occurred. These bits are set whether or not the interrupt is masked in the GPTMIMR register. However, whether these set raw interrupts can be sent to the interrupt controller to be further processed, it depends on whether the corresponding bits on the GPTMIMR register are set (enabled) or not (disabled). Only for those bits that have been set on the GPTMIMR register, they can be sent to the NVIC. The bit field and functions for this register are similar to those in the GPTMIMR register. If a GPTM-related raw interrupt is generated, the corresponding bit on this register is set to 1. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR register.
 +
 
 +
 
 +
{| class="wikitable" style="margin: auto;"
 +
|-
 +
! Bit !! Name !! Description
 +
|-
 +
| 0 || TATORIS || Timer A Time-out Raw interrupt (0: not occurred, 1: occurred)
 +
|-
 +
| 1 || CAMRIS || Timer A Capture Mode Match Raw Interrupt (0: not occurred, 1: occurred)
 +
|-
 +
| 2 || CAERIS || Timer A Capture Mode Event Raw Interrupt (0: not occurred, 1: occurred)
 +
|-
 +
| 3 || RTCRIS || RTC Raw Interrupt(0: not occurred, 1: occurred)
 +
|-
 +
| 4 ||TAMRIS || Timer A Match Raw Interrupt
 +
|-
 +
| 8 || TBTORIS || Timer B Time-out Raw interrupt (0: not occurred, 1: occurred)
 +
|-
 +
| 9 || CBMRIS || Timer B Capture Mode Match Raw Interrupt (0: not occurred, 1: occurred)
 +
|-
 +
| 10 || CBERIS || Timer B Capture Mode Event Raw Interrupt (0: not occurred, 1: occurred)
 +
|-
 +
| 11 || TBMRIS || Timer B Match Raw Interrupt
 +
|-
 +
| 16 || WUERIS || 32/64-Bit Wide GPTM Write Update Error Raw Interrupt Status
 +
|}
  
To perform this periodic interrupt for each 65.536 ms, one needs to:
+
=== GPTM Masked Interrupt Status Register (GPTMMIS) ===
# Enable and clock the Timer0A for GPTM Block 0.
+
# Enable and clock the GPIO Port B.
+
# Disable the Timer0A module before any configuration can be performed.
+
# Configure the Timer0A to work as a 16-bit count-down periodic counter.
+
# Load 65535 (65536 – 1) into the GPTMTAILR register as the start value since we want to get the maximum period of time, which is 65.536 ms, for each period.
+
# Load 15 (16 – 1) into the GPTMTAPR register as a prescale value. After this 16 MHz system clock is divided by this prescaler (16), the working clock for this counter is 1 MHz with a 1-μs period.
+
# Clear any previous timeout interrupt for Timer0A by writing 1 to an appropriate bit in the GPTMICR register.
+
# Enable Timer0A timeout interrupt by writing 1 to an appropriate bit in the GPTMIMR register.
+
# Use NVIC_PRI4_R (Bit 31 - 29 ) to set the interrupt priority level as 3 for the Timer0A.
+
# Use NVIC_EN0_R (IRQ19) to enable the timeout interrupt for the Timer0A.
+
# Enable the Timer0A module after these configuration and the Timer0A begins to count.
+
# Use EnableInterrupts() function to globally enable all interrupts.
+
# Use an infinitive while() loop to wait for any interrupt coming.
+
  
In addition to the main program, one also needs to build the Timer0A interrupt handler:
+
[[image:tm4c_gptmmis_r.png|center]]
# Clear the timeout interrupt for Timer0A by writing 1 to an appropriate bit in the GPTMICR register to enable it to be generated in the future.
+
# Turn on the related LED via GPIO Port F.
+
  
'''Task 3''': '''Use Timer1A and Timer2A timeout events to trigger interrupts'''.
+
Similar to the GPTMIMR register, this 32-bit register only used the lower 10 bits to monitor and make a responded interrupt if a GPTM related interrupt is occurred and has been responded. The bit field and functions for this register is similar to those in the GPTMIMR register. A value of 1 on a bit in this register indicates that the corresponding interrupt has occurred and has received a response. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR register.
* Configure Timer1A to timeout once every second. In the interrupt handler, toggle the red LED.
+
* Configure Timer2A to timeout at 10 Hz. In the interrupt handler, toggle the green LED.
+
* The infinite loop in the main program should blink the blue LED while the interrupts are going on.
+
  
 +
=== GPTM Interrupt Clear Register (GPTMICR) ===
  
 +
[[image:tm4c_gptmicr_r.png|center]]
  
[[File:prev.gif|left|link=EmSys:TM4C123 Use of GPTM with GPIO Pins]]
+
Similar to GPTMIMR register, this 32-bit register only used the lower 10 bits to clear related responded interrupts if the
[[File:home.gif|center|link=http://shukra.dese.iisc.ernet.in/edwiki/Main_Page]]
+
GPTM-related interrupts have received a response and have been processed. This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. All processed or responded interrupts must be cleared by using this register. Otherwise the responded interrupt cannot be generated again in the future if it is not cleared. The bit field and functions for this register is similar to those in the GPTMIMR register.

Latest revision as of 05:08, 12 March 2020

Timer Interrupt Programming

In the previous article, we showed how to program the timers. In those programming examples, we used polling to see if a timeout event occurred. In this section, we give interrupt-based version of those programs. Examine the earlier programs, we could run those programs only one at a time since we have to monitor the timer flag continuously. By using interrupt, we can run several of timer programs all at the same. To do that, we need to enable the timer interrupts using the GPTMIMR (GPTM Interrupt Mask) register.

Timers A and B Interrupt and Configuration Register Group

Six registers are used to control and handle interrupts of the Timers A and B:

  • GPTM Interrupt Mask Register (GPTMIMR)
  • GPTM Raw Interrupt Status Register (GPTMRIS)
  • GPTM Masked Interrupt Status Register (GPTMMIS)
  • GPTM Interrupt Clear Register (GPTMICR)
  • GPTM Synchronize Register (GPTMSYNC)
  • GPTM Peripheral Properties Register (GPTMPP)

GPTM Interrupt Mask Register (GPTMIMR)

Tm4c gptm imr.png


Bit Name Description
0 TATOIM Timer A Time-out Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
1 CAMIM Timer A Capture Mode Match Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
2 CAEIM Timer A Capture Mode Event Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
3 RTCIM RTC Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
4 TAMIM Timer A Match Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
8 TBTOIM Timer B Time-out Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
9 CBMIM Timer B Capture Mode Match Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
10 CBEIM Timer B Capture Mode Event Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
11 TBMIM Timer B Match Interrupt Mask (0: interrupt is disabled, 1: interrupt is enabled)
16 WUEIM 32/64-Bit Wide GPTM Write Update Error Interrupt Mask (0: disabled, 1: enabled)
Table 10.1: GPTM Interrupt Mask (GPTMIMR)


IRQ21 is assigned to Timer1A and IRQ23 to Timer2A. The following will enable these timers in NVIC:

NVIC_EN0_R |= 0x00200000;   /* enable IRQ21  */
NVIC_EN0_R |= 0x00800000;   /* enable IRQ23 */

GPTM Raw Interrupt Status Register (GPTMRIS)

Tm4c gptmris r.png


This 32-bit register only used the lower 10 bits to monitor and set a raw or internal interrupt if a GPTM-related raw interrupt occurred. These bits are set whether or not the interrupt is masked in the GPTMIMR register. However, whether these set raw interrupts can be sent to the interrupt controller to be further processed, it depends on whether the corresponding bits on the GPTMIMR register are set (enabled) or not (disabled). Only for those bits that have been set on the GPTMIMR register, they can be sent to the NVIC. The bit field and functions for this register are similar to those in the GPTMIMR register. If a GPTM-related raw interrupt is generated, the corresponding bit on this register is set to 1. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR register.


Bit Name Description
0 TATORIS Timer A Time-out Raw interrupt (0: not occurred, 1: occurred)
1 CAMRIS Timer A Capture Mode Match Raw Interrupt (0: not occurred, 1: occurred)
2 CAERIS Timer A Capture Mode Event Raw Interrupt (0: not occurred, 1: occurred)
3 RTCRIS RTC Raw Interrupt(0: not occurred, 1: occurred)
4 TAMRIS Timer A Match Raw Interrupt
8 TBTORIS Timer B Time-out Raw interrupt (0: not occurred, 1: occurred)
9 CBMRIS Timer B Capture Mode Match Raw Interrupt (0: not occurred, 1: occurred)
10 CBERIS Timer B Capture Mode Event Raw Interrupt (0: not occurred, 1: occurred)
11 TBMRIS Timer B Match Raw Interrupt
16 WUERIS 32/64-Bit Wide GPTM Write Update Error Raw Interrupt Status

GPTM Masked Interrupt Status Register (GPTMMIS)

Tm4c gptmmis r.png

Similar to the GPTMIMR register, this 32-bit register only used the lower 10 bits to monitor and make a responded interrupt if a GPTM related interrupt is occurred and has been responded. The bit field and functions for this register is similar to those in the GPTMIMR register. A value of 1 on a bit in this register indicates that the corresponding interrupt has occurred and has received a response. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR register.

GPTM Interrupt Clear Register (GPTMICR)

Tm4c gptmicr r.png

Similar to GPTMIMR register, this 32-bit register only used the lower 10 bits to clear related responded interrupts if the GPTM-related interrupts have received a response and have been processed. This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. All processed or responded interrupts must be cleared by using this register. Otherwise the responded interrupt cannot be generated again in the future if it is not cleared. The bit field and functions for this register is similar to those in the GPTMIMR register.