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[[image:tm4c_gptm_imr.png|center]]
 
[[image:tm4c_gptm_imr.png|center]]
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{| class="wikitable" style="margin: auto;"
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|-
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! Bit !! Name !! Description
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|-
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| 0 || TATOIM || Timer A Time-out Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
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|-
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| 1 || CAMIM || Timer A Capture Mode Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
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|-
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| 2 || CAEIM || Timer A Capture Mode Event Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
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|-
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| 3 || RTCIM || RTC Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
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|-
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| 4 || TAMIM || Timer A Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
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|-
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| 8 || TBTOIM || Timer B Time-out Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
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|-
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| 9 || CBMIM || Timer B Capture Mode Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
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|-
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| 10 || CBEIM || Timer B Capture Mode Event Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
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|-
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| 11 || TBMIM || Timer B Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
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|-
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| 16 || WUEIM || 32/64-Bit Wide GPTM Write Update Error Interrupt Mask (0:disabled, 1:enabled)
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|}
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<div style="text-align: center;">'''Table 10.1''': GPTM Interrupt Mask (GPTMIMR)</div>
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IRQ21 is assigned to Timer1A and IRQ23 to Timer2A. The following will enable these timers in NVIC:
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NVIC->ISER[0] |= 0x00200000;/* enable IRQ21 (D21 of ISER[0]) */
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NVIC->ISER[0] |= 0x00800000; /* enable IRQ23 (D23 of ISER[0]) */

Revision as of 05:41, 27 February 2018

Timer Interrupt Programming

In the previous article, we showed how to program the timers. In those programming examples, we used polling to see if a timeout event occurred. In this section, we give interrupt-based version of those programs. Examine the earlier programs, we could run those programs only one at a time since we have to monitor the timer flag continuously. By using interrupt, we can run several of timer programs all at the same. To do that, we need to enable the timer interrupts using the GPTMIMR (GPTM Interrupt Mask) register.

Tm4c gptm imr.png
Bit Name Description
0 TATOIM Timer A Time-out Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
1 CAMIM Timer A Capture Mode Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
2 CAEIM Timer A Capture Mode Event Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
3 RTCIM RTC Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
4 TAMIM Timer A Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
8 TBTOIM Timer B Time-out Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
9 CBMIM Timer B Capture Mode Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
10 CBEIM Timer B Capture Mode Event Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
11 TBMIM Timer B Match Interrupt Mask (0:interrupt is disabled, 1:interrupt is enabled)
16 WUEIM 32/64-Bit Wide GPTM Write Update Error Interrupt Mask (0:disabled, 1:enabled)
Table 10.1: GPTM Interrupt Mask (GPTMIMR)

IRQ21 is assigned to Timer1A and IRQ23 to Timer2A. The following will enable these timers in NVIC:

NVIC->ISER[0] |= 0x00200000;/* enable IRQ21 (D21 of ISER[0]) */
NVIC->ISER[0] |= 0x00800000; /* enable IRQ23 (D23 of ISER[0]) */