Tm4clib-rcc-defines
From EdWiki
Enumeration Types
Defined Constants and Types for the TM4C Reset and Clock Control
osc_src
enum osc_src
Oscillator source values.
Possible values of the oscillator source.
| Enumerator |
|---|
| OSCSRC_MOSC |
| OSCSRC_PIOSC |
| OSCSRC_PIOSC_D4 |
| OSCSRC_30K_INT |
| OSCSRC_32K_EXT |
pwm_clkdiv
enum pwm_clkdiv
PWM clock divisor values.
Possible values of the binary divisor used to predivide the system clock down for use as the timing reference for the PWM module
| Enumerator |
|---|
| PWMDIV_2 |
| PWMDIV_4 |
| PWMDIV_8 |
| PWMDIV_16 |
| PWMDIV_32 |
| PWMDIV_32 |
xtal_t
enum xtal_t
Predefined crystal values.
Predefined crystal values for the XTAL field in SYSCTL_RCC. Using these predefined values in the XTAL field, the SYSCTL_PLLFREQ0 and SYSCTL_PLLFREQ1 are automatically adjusted in hardware to provide a PLL clock of 400MHz.
| Enumerator |
|---|
| XTAL_4M |
| XTAL_4M_096 |
| XTAL_4M_9152 |
| XTAL_5M |
| TAL_5M_12 |
| XTAL_6M |
| XTAL_6M_144 |
| XTAL_7M_3728 |
| XTAL_8M |
| XTAL_8M_192 |
| XTAL_10M |
| XTAL_12M_288 |
| XTAL_13M_56 |
| XTAL_14M_31818 |
| XTAL_16M |
| XTAL_16M_384 |
| XTAL_18M |
| XTAL_20M |
| XTAL_24M |
| XTAL_25M |
tm4c_clken
enum tm4c_clken
Clock enable definitions.
The definitions are specified in the form 31:5 register offset from SYSCTL_BASE for the clock register 4:0 bit offset for the given peripheral
The names have the form [clock_type]_[periph_type]_[periph_number] Where clock_type is RCC for run clock SCC for sleep clock DCC for deep-sleep clock
| Enumerator |
|---|
| RCC_WD0 |
| RCC_WD1 |
| RCC_TIMER0 |
| RCC_TIMER1 |
| RCC_TIMER2 |
| RCC_TIMER3 |
| RCC_TIMER4 |
| RCC_TIMER5 |
| RCC_GPIOA |
| RCC_GPIOB |
| RCC_GPIOC |
| RCC_GPIOD |
| RCC_GPIOE |
| RCC_GPIOF |
| RCC_GPIOG |
| RCC_GPIOH |
| RCC_GPIOJ |
| RCC_GPIOK |
| RCC_GPIOL |
| RCC_GPIOM |
| RCC_GPION |
| RCC_GPIOP |
| RCC_GPIOQ |
| RCC_DMA |
| RCC_HIB |
| RCC_UART0 |
| RCC_UART1 |
| RCC_UART2 |
| RCC_UART3 |
| RCC_UART4 |
| RCC_UART5 |
| RCC_UART6 |
| RCC_UART7 |
| RCC_SSI0 |
| RCC_SSI1 |
| RCC_SSI2 |
| RCC_SSI3 |
| RCC_I2C0 |
| RCC_I2C1 |
| RCC_I2C2 |
| RCC_I2C3 |
| RCC_I2C4 |
| RCC_I2C5 |
| RCC_USB0 |
| RCC_CAN0 |
| RCC_CAN1 |
| RCC_ADC0 |
| RCC_ADC1 |
| RCC_ACMP0 |
| RCC_PWM0 |
| RCC_PWM1 |
| RCC_QEI0 |
| RCC_QEI1 |
| RCC_EEPROM0 |
| RCC_WTIMER0 |
| RCC_WTIMER1 |
| RCC_WTIMER2 |
| RCC_WTIMER3 |
| RCC_WTIMER4 |
| RCC_WTIMER5 |
| SCC_WD0 |
| SCC_WD1 |
| SCC_TIMER0 |
| SCC_TIMER1 |
| SCC_TIMER2 |
| SCC_TIMER3 |
| SCC_TIMER4 |
| SCC_TIMER5 |
| SCC_GPIOA |
| SCC_GPIOB |
| SCC_GPIOC |
| SCC_GPIOD |
| SCC_GPIOE |
| SCC_GPIOF |
| SCC_GPIOG |
| SCC_GPIOH |
| SCC_GPIOJ |
| SCC_GPIOK |
| SCC_GPIOL |
| SCC_GPIOM |
| SCC_GPION |
| SCC_GPIOP |
| SCC_GPIOQ |
| SCC_DMA |
| SCC_HIB |
| SCC_UART0 |
| SCC_UART1 |
| SCC_UART2 |
| SCC_UART3 |
| SCC_UART4 |
| SCC_UART5 |
| SCC_UART6 |
| SCC_UART7 |
| SCC_SSI0 |
| SCC_SSI1 |
| SCC_SSI2 |
| SCC_SSI3 |
| SCC_I2C0 |
| SCC_I2C1 |
| SCC_I2C2 |
| SCC_I2C3 |
| SCC_I2C4 |
| SCC_I2C5 |
| SCC_USB0 |
| SCC_CAN0 |
| SCC_CAN1 |
| SCC_ADC0 |
| SCC_ADC1 |
| SCC_ACMP0 |
| SCC_PWM0 |
| SCC_PWM1 |
| SCC_QEI0 |
| SCC_QEI1 |
| SCC_EEPROM0 |
| SCC_WTIMER0 |
| SCC_WTIMER1 |
| SCC_WTIMER2 |
| SCC_WTIMER3 |
| SCC_WTIMER4 |
| SCC_WTIMER5 |
| DCC_WD0 |
| DCC_WD1 |
| DCC_TIMER0 |
| DCC_TIMER1 |
| DCC_TIMER2 |
| DCC_TIMER3 |
| DCC_TIMER4 |
| DCC_TIMER5 |
| DCC_GPIOA |
| DCC_GPIOB |
| DCC_GPIOC |
| DCC_GPIOD |
| DCC_GPIOE |
| DCC_GPIOF |
| DCC_GPIOG |
| DCC_GPIOH |
| DCC_GPIOJ |
| DCC_GPIOK |
| DCC_GPIOL |
| DCC_GPIOM |
| DCC_GPION |
| DCC_GPIOP |
| DCC_GPIOQ |
| DCC_DMA |
| DCC_HIB |
| DCC_UART0 |
| DCC_UART1 |
| DCC_UART2 |
| DCC_UART3 |
| DCC_UART4 |
| DCC_UART5 |
| DCC_UART6 |
| DCC_UART7 |
| DCC_SSI0 |
| DCC_SSI1 |
| DCC_SSI2 |
| DCC_SSI3 |
| DCC_I2C0 |
| DCC_I2C1 |
| DCC_I2C2 |
| DCC_I2C3 |
| DCC_I2C4 |
| DCC_I2C5 |
| DCC_USB0 |
| DCC_CAN0 |
| DCC_CAN1 |
| DCC_ADC0 |
| DCC_ADC1 |
| DCC_ACMP0 |
| DCC_PWM0 |
| DCC_PWM1 |
| DCC_QEI0 |
| DCC_QEI1 |
| DCC_EEPROM0 |
| DCC_WTIMER0 |
| DCC_WTIMER1 |
| DCC_WTIMER2 |
| DCC_WTIMER3 |
| DCC_WTIMER4 |
| DCC_WTIMER5 |