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Tm4clib-rcc-functions

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RCC - High-level clock control API

rcc_change_pll_divisor()

void rcc_change_pll_divisor(uint8_t pll_div400)
Change the PLL divisor.

Changes the divisor applied to the 400MHz PLL clock. The PLL must have previously been configured by selecting an appropriate XTAL value, and turning on the PLL. This function does not reconfigure the XTAL value or oscillator source. It only changes the PLL divisor.

The PLL is bypassed before modifying the divisor, and the function blocks until the PLL is locked, then the bypass is disabled, before returning.

Parameters
[in] pll_div400 The clock divisor to apply to the 400MHz PLL clock.

See also
xtal_t

rcc_get_system_clock_frequency()

uint32_t rcc_get_system_clock_frequency(void)
Get the system clock frequency.

Returns
System clock frequency in Hz

rcc_sysclk_config()

void rcc_sysclk_config(enum osc_src src, enum xtal_t xtalt, uint8_t pll_div400)
Configure the system clock source.

Sets up the system clock, including configuring the oscillator source, and PLL to acheve the desired system clock frequency. Where applicable, The LM4F clock API uses the new RCC2 register to configure clock parameters.

Enables the main oscillator if the clock source is OSCSRC_MOSC. If the main oscillator was previously enabled, it will not be disabled. If desired, it can be separately disabled by a call to rcc_disable_main_osc().

Configures the system clock to run from the 400MHz PLL with a divisor of pll_div400 applied. If pll_div400 is 0, then the PLL is disabled, and the system clock is configured to run off a "raw" clock. If the PLL was previously powered on, it will not be disabled. If desired, it can de powered off by a call to rcc_pll_off().

Parameters
[in] src osc_src Oscillator from where to derive the system clock.
[in] xtalt xtal_t Type of crystal connected to the OSCO/OSCI pins
[in] pll_div400 The clock divisor to apply to the 400MHz PLL clock. If 0, then the PLL is disabled, and the system runs off a "raw" clock.
Returns System clock frequency in Hz

periph_enable_clock()

void periph_enable_clock(enum tm4c_clken periph)
Enable the clock source for the peripheral.

Parameters
[in] periph → peripheral and clock type to enable

periph_disable_clock()

void periph_disable_clock(enum tm4c_clken periph)
Disable the clock source for the peripheral.

Parameters
[in] periph → peripheral and clock type to enable

RCC - Low-level clock control API

rcc_configure_xtal()

void rcc_configure_xtal(enum xtal_t xtal)
Configure the crystal type connected to the device.

Configure the crystal type connected between the OSCO and OSCI pins by writing the appropriate value to the XTAL field in SYSCTL_RCC. The PLL parameters are automatically adjusted in hardware to provide a PLL clock of 400MHz.

Parameters
[in] xtal predefined crystal type

rcc_disable_internal_osc()

void rcc_disable_internal_osc(void)
Disable the internal oscillator.

Sets the IOSCDIS bit in SYSCTL_RCC, disabling the internal oscillator.

rcc_disable_main_osc()

void rcc_disable_main_osc(void)
Disable the main oscillator.

Sets the IOSCDIS bit in SYSCTL_RCC, disabling the main oscillator.

rcc_enable_internal_osc()

void rcc_enable_internal_osc(void)
Enable the internal oscillator.

Clears the IOSCDIS bit in SYSCTL_RCC, enabling the internal oscillator.

rcc_enable_main_osc()

void rcc_enable_main_osc(void)
Enable the main oscillator.

Clears the MOSCDIS bit in SYSCTL_RCC, enabling the main oscillator.

rcc_enable_rcc2()

void rcc_enable_rcc2(void)
Enable the use of SYSCTL_RCC2 register for clock control.

Enables the USERCC2 bit in SYSCTTL_RCC2. Settings in SYSCTL_RCC2 will override settings in SYSCTL_RCC. This function must be called before other calls to manipulate the clock, as libopencm3 uses the SYSCTL_RCC2 register.

rcc_pll_bypass_disable()

void rcc_pll_bypass_disable(void)
Disable the PLL bypass and use the PLL clock.

Clear BYPASS2 in SYSCTL_RCC2. The system clock is derived from the PLL clock divided by the divisor specified in SYSDIV2.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

rcc_pll_bypass_enable()

void rcc_pll_bypass_enable(void)
Enable the PLL bypass and use the oscillator clock.

Set BYPASS2 in SYSCTL_RCC2. The system clock is derived from the oscillator clock divided by the divisor specified in SYSDIV2.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

rcc_pll_off()

void rcc_pll_off(void)
Power down the main PLL.

Sets the SYSCTL_RCC2_PWRDN2 in SYSCTL_RCC2 to power down the PLL.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

rcc_pll_on()

void rcc_pll_on(void)
Power up the main PLL.

Clears the PWRDN2 in SYSCTL_RCC2 to power on the PLL.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

rcc_set_osc_source()

void rcc_set_osc_source(enum osc_src src)
Set the oscillator source to be used by the system clock.

Set the clock source for the system clock.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

rcc_set_pll_divisor()

void rcc_set_pll_divisor(uint8_t div400)
Set the PLL clock divisor (from 400MHz)

Set the binary divisor used to predivide the system clock down for use as the timing reference for the PWM module. The divisor is expected to be a divisor from 400MHz, not 200MHz. The DIV400 is also set.

Specifies the divisor that used to generate the system clock from either the PLL output or the oscillator source (depending on the BYPASS2 bit in SYSCTL_RCC2). SYSDIV2 is used for the divisor when both the USESYSDIV bit in SYSCTL_RCC is set.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

rcc_set_pwm_divisor()

void rcc_set_pwm_divisor(enum pwm_clkdiv div)
Set the PWM unit clock divisor.

Set the binary divisor used to predivide the system clock down for use as the timing reference for the PWM module.

Parameters
[in] div clock divisor to use
See also
pwm_clkdiv_t

rcc_usb_pll_off()

void rcc_usb_pll_off(void)
Power down the USB PLL.

Sets the USBPWRDN in SYSCTL_RCC2 to power down the USB PLL.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

rcc_usb_pll_on()

void rcc_usb_pll_on(void)
Power up the USB PLL.

Clears the USBPWRDN in SYSCTL_RCC2 to power on the USB PLL.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

rcc_wait_for_pll_ready()

void rcc_wait_for_pll_ready(void)
Wait for main PLL to lock.

Waits until the LOCK bit in SYSCTL_PLLSTAT is set. This guarantees that the PLL is locked, and ready to use.

tm4c_rcc_sysclk_freq

uint32_t lm4f_rcc_sysclk_freq = 16000000
System clock frequency.

This variable is provided to keep track of the system clock frequency. It should be updated every time the system clock is changed via the fine-grained mechanisms. The initial value is 16MHz, which corresponds to the clock of the internal 16MHz oscillator.

High-level routines update the system clock automatically. For read access, it is recommended to access this variable via

rcc_get_system_clock_frequency();

If write access is desired (i.e. when changing the system clock via the fine-grained mechanisms), then include the following line in your code:

extern uint32_t tm4c_rcc_sysclk_freq;

xtal_to_freq()

uint32_t xtal_to_freq(enum xtal_t xtal)
Get the clock frequency corresponding to a given XTAL value.