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Tm4clib-uart-defines

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Revision as of 07:06, 31 October 2018 by Jshankar (Talk | contribs)

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Constants and Types

UART_9BITADDR

#define UART_9BITADDR(uart_base)	   MMIO32((uart_base) + 0xA4)

UART_9BITAMASK

#define UART_9BITAMASK(uart_base)	   MMIO32((uart_base) + 0xA8)

UART_CC

#define UART_CC(uart_base)	   MMIO32((uart_base) + 0xFC8)

UART_CC_CS_MASK

#define UART_CC_CS_MASK   (0xF << 0) /* UART baud clock source. */

UART_CC_CS_PIOSC

#define UART_CC_CS_PIOSC   (0x5 << 0)

UART_CC_CS_SYSCLK

#define UART_CC_CS_SYSCLK   (0x0 << 0)

UART_CTL

#define UART_CTL(uart_base)	   MMIO32((uart_base) + 0x30)

UART_CTL_CTSEN

#define UART_CTL_CTSEN   (1 << 15)  /* Enable Clear To Send */

UART_CTL_DTR

#define UART_CTL_DTR   (1 << 10)    /* Data terminal ready. */ 

UART_CTL_EOT

#define UART_CTL_EOT   (1 << 4)    /* End of transmission. */

UART_CTL_HSE

#define UART_CTL_HSE   (1 << 5)    /* High speed Enable. */

UART_CTL_LBE

#define UART_CTL_LBE   (1 << 7)    /* Loop back enable. */

UART_CTL_LIN

#define UART_CTL_LIN   (1 << 6)    /* LIN mode enable. */

UART_CTL_RTS

#define UART_CTL_RTS   (1 << 11)   /* Request To Send. */

UART_CTL_RTSEN

#define UART_CTL_RTSEN   (1 << 14)    /* Enable Request To Send. */

UART_CTL_RXE

#define UART_CTL_RXE   (1 << 9)    /* Rx Enable. */

UART_CTL_SIREN

#define UART_CTL_SIREN   (1 << 1)    /* SIR enable. */

UART_CTL_SIRLIP

#define UART_CTL_SIRLIP   (1 << 2)    /* SIR low-power mode. */

UART_CTL_SMART

#define UART_CTL_SMART   (1 << 3)    /* ISO 7816 Smart Card support. */

UART_CTL_TXE

#define UART_CTL_TXE   (1 << 8)    /* Tx Enable. */

UART_CTL_UARTEN

#define UART_CTL_UARTEN   (1 << 0)    /* UART enable. */

UART_DMACTL

#define UART_DMACTL(uart_base)	   MMIO32((uart_base) + 0x48)

UART_DMACTL_DMAERR

#define UART_DMACTL_DMAERR   (1 << 2)    /* DMA on error. */

UART_DMACTL_RXDMAE

#define UART_DMACTL_RXDMAE   (1 << 0)    /* Receive DMA enable. */

UART_DMACTL_TXDMAE

#define UART_DMACTL_TXDMAE   (1 << 1)    /* Transmit DMA enable. */

UART_DR

#define UART_DR(uart_base)	   MMIO32((uart_base) + 0x00)

UART_DR_BE

#define UART_DR_BE   (1 << 10)    /* Break Error. */

UART_DR_DATA_MASK

#define UART_DR_DATA_MASK   (0xFF << 0)    /* Data transmitted or received. */

UART_DR_FE

#define UART_DR_FE   (1 << 8)    /* Framing Error. */

UART_DR_OE

#define UART_DR_OE   (1 << 11)    /* Overrun Error. */

UART_DR_PE

#define UART_DR_PE   (1 << 9)    /* Parity Error. */

UART_ECR

#define UART_ECR(uart_base)	   MMIO32((uart_base) + 0x04)

UART_FBRD

#define UART_FBRD(uart_base)	   MMIO32((uart_base) + 0x28)

UART_FR

#define UART_FR(uart_base)	   MMIO32((uart_base) + 0x18)

UART_FR_BUSY

#define UART_FR_BUSY   (1 << 3)    /* UART Busy. */

UART_FR_CTS

#define UART_FR_CTS   (1 << 0)     /* Clear To Send. */

UART_FR_RXFE

#define UART_FR_RXFE   (1 << 4)    /* Rx FIFO empty. */

UART_FR_RXFF

#define UART_FR_RXFF   (1 << 6)    /* Rx FIFO full. */

UART_FR_TXFE

#define UART_FR_TXFE   (1 << 7)    /* Tx FIFO empty. */

UART_FR_TXFF

#define UART_FR_TXFF   (1 << 5)    /* Tx FIFO full. */

UART_IBRD

#define UART_IBRD(uart_base)	   MMIO32((uart_base) + 0x24)

UART_ICR

#define UART_ICR(uart_base)	   MMIO32((uart_base) + 0x44)

UART_IFLS

#define UART_IFLS(uart_base)	   MMIO32((uart_base) + 0x34)

UART_IFLS_RXIFLSEL_1_2

#define UART_IFLS_RXIFLSEL_1_2   (2 << 3)

UART_IFLS_RXIFLSEL_1_4

#define UART_IFLS_RXIFLSEL_1_4   (1 << 3)

UART_IFLS_RXIFLSEL_1_8

#define UART_IFLS_RXIFLSEL_1_8   (0 << 3)

UART_IFLS_RXIFLSEL_3_4

#define UART_IFLS_RXIFLSEL_3_4   (3 << 3)

UART_IFLS_RXIFLSEL_7_8

#define UART_IFLS_RXIFLSEL_7_8   (4 << 3)

UART_IFLS_RXIFLSEL_MASK

#define UART_IFLS_RXIFLSEL_MASK   (7 << 3)    /* UART Rx interrupt FIFO level select. */

UART_IFLS_TXIFLSEL_1_2

#define UART_IFLS_TXIFLSEL_1_2   (2 << 0)

UART_IFLS_TXIFLSEL_1_4

#define UART_IFLS_TXIFLSEL_1_4   (3 << 0)

UART_IFLS_TXIFLSEL_1_8

#define UART_IFLS_TXIFLSEL_1_8   (4 << 0)

UART_IFLS_TXIFLSEL_3_4

#define UART_IFLS_TXIFLSEL_3_4   (1 << 0)

UART_IFLS_TXIFLSEL_7_8

#define UART_IFLS_TXIFLSEL_7_8   (0 << 0)

UART_IFLS_TXIFLSEL_MASK

#define UART_IFLS_TXIFLSEL_MASK   (7 << 0)    /* UART Tx interrupt FIFO level select. */

UART_ILPR

#define UART_ILPR(uart_base)	   MMIO32((uart_base) + 0x20)

UART_IM

#define UART_IM(uart_base)	   MMIO32((uart_base) + 0x38)

UART_IM_9BITIM

#define UART_IM_9BITIM   (1 << 12)    /* 9-bit mode interrupt mask */

UART_IM_BEIM

#define UART_IM_BEIM   (1 << 9)    /* Break error interrupt mask. */

UART_IM_CTSIM

#define UART_IM_CTSIM   (1 << 1)   /* Clear To Send modem interrupt mask. */

UART_IM_DCDIM

#define UART_IM_DCDIM   (1 << 2)    /* Data Carrier Detect modem interrupt mask. */

UART_IM_DSRIM

#define UART_IM_DSRIM   (1 << 3)    /* Data Set Ready modem interrupt mask. */

UART_IM_FEIM

#define UART_IM_FEIM   (1 << 7)    /* Framing error interrupt mask. */

UART_IM_LME1IM

#define UART_IM_LME1IM   (1 << 14)    /* LIN mode edge 1 interrupt mask. */

UART_IM_LME5IM

#define UART_IM_LME5IM   (1 << 15)    /* LIN mode edge 5 interrupt mask. */

UART_IM_LMSBIM

#define UART_IM_LMSBIM   (1 << 13)    /* LIN mode sync break interrupt mask. */

UART_IM_OEIM

#define UART_IM_OEIM   (1 << 10)    /* Overrun error interrupt mask. */

UART_IM_PEIM

#define UART_IM_PEIM   (1 << 8)    /* Parity error interrupt mask. */

UART_IM_RIIM

#define UART_IM_RIIM   (1 << 0)    /* Ring Indicator modem interrupt mask. */

UART_IM_RTIM

#define UART_IM_RTIM   (1 << 6)    /* Receive time-out interrupt mask. */

UART_IM_RXIM

#define UART_IM_RXIM   (1 << 4)    /* Receive interrupt mask. */

UART_IM_TXIM

#define UART_IM_TXIM   (1 << 5)    /* Transmit interrupt mask. */

UART_LCRH

#define UART_LCRH(uart_base)	   MMIO32((uart_base) + 0x2C)

UART_LCRH_BRK

#define UART_LCRH_BRK   (1 << 0)    /* Send break. */

UART_LCRH_EPS

#define UART_LCRH_EPS   (1 << 2)    /* Even parity select. */

UART_LCRH_FEN

#define UART_LCRH_FEN   (1 << 4)    /* Enable FIFOs. */

UART_LCRH_PEN

#define UART_LCRH_PEN   (1 << 1)    /* Parity enable. */

UART_LCRH_SPS

#define UART_LCRH_SPS   (1 << 7)    /* Stick parity select. */

UART_LCRH_STP2

#define UART_LCRH_STP2   (1 << 3)    /* Two stop bits select. */

UART_LCRH_WLEN_5

#define UART_LCRH_WLEN_5   (0 << 5)

UART_LCRH_WLEN_6

#define UART_LCRH_WLEN_6   (1 << 5)

UART_LCRH_WLEN_7

#define UART_LCRH_WLEN_7   (2 << 5)

UART_LCRH_WLEN_8

#define UART_LCRH_WLEN_8   (3 << 5)

UART_LCRH_WLEN_MASK

#define UART_LCRH_WLEN_MASK   (3 << 5)    /* Word length. */

UART_LCTL

#define UART_LCTL(uart_base)	   MMIO32((uart_base) + 0x90)

UART_LCTL_BLEN_13T

#define UART_LCTL_BLEN_13T   (0 << 4)

UART_LCTL_BLEN_14T

#define UART_LCTL_BLEN_14T   (1 << 4)

UART_LCTL_BLEN_15T

#define UART_LCTL_BLEN_15T   (2 << 4)

UART_LCTL_BLEN_16T

#define UART_LCTL_BLEN_16T   (3 << 4)

UART_LCTL_BLEN_MASK

#define UART_LCTL_BLEN_MASK   (3 << 4)    /* Sync break length. */

UART_LCTL_MASTER

#define UART_LCTL_MASTER   (1 << 0)     /* LIN master enable. */

UART_LSS

#define UART_LSS(uart_base)	   MMIO32((uart_base) + 0x94)

UART_LTIM

#define UART_LTIM(uart_base)	   MMIO32((uart_base) + 0x98)

UART_MIS

#define UART_MIS(uart_base)	   MMIO32((uart_base) + 0x40)

UART_PCELL_ID0

#define UART_PCELL_ID0	(uart_base)	   MMIO32((uart_base) + 0xFF0)

UART_PCELL_ID1

#define UART_PCELL_ID1(uart_base)	   MMIO32((uart_base) + 0xFF4)

UART_PCELL_ID2

#define UART_PCELL_ID2	(uart_base)	   MMIO32((uart_base) + 0xFF8)

UART_PCELL_ID3

#define UART_PCELL_ID3(uart_base)	   MMIO32((uart_base) + 0xFFC)

UART_PERIPH_ID0

#define UART_PERIPH_ID0(uart_base)	   MMIO32((uart_base) + 0xFE0)

UART_PERIPH_ID1

#define UART_PERIPH_ID1(uart_base)	   MMIO32((uart_base) + 0xFE4)

UART_PERIPH_ID2

#define UART_PERIPH_ID2(uart_base)	   MMIO32((uart_base) + 0xFE8)

UART_PERIPH_ID3

#define UART_PERIPH_ID3(uart_base)	   MMIO32((uart_base) + 0xFEC)

UART_PERIPH_ID4

#define UART_PERIPH_ID4(uart_base)	   MMIO32((uart_base) + 0xFD0)

UART_PERIPH_ID5

#define UART_PERIPH_ID5(uart_base)	   MMIO32((uart_base) + 0xFD4)

UART_PERIPH_ID6

#define UART_PERIPH_ID6(uart_base)	   MMIO32((uart_base) + 0xFD8)

UART_PERIPH_ID7

#define UART_PERIPH_ID7(uart_base)	   MMIO32((uart_base) + 0xFDC)

UART_PP

#define UART_PP(uart_base)	   MMIO32((uart_base) + 0xFC0)

UART_RIS

#define UART_RIS(uart_base)	   MMIO32((uart_base) + 0x3C)

UART_RSR

#define UART_RSR(uart_base)	   MMIO32((uart_base) + 0x04)

UART_RSR_BE

#define UART_RSR_BE   (1 << 2)    /* Break Error. */

UART_RSR_FE

#define UART_RSR_FE   (1 << 0)    /* Framing Error. */

UART_RSR_OE

#define UART_RSR_OE   (1 << 3)    /* Overrun Error. */

UART_RSR_PE

#define UART_RSR_PE   (1 << 1)    /* Parity Error. */

UART_UART_9BITADDR_9BITEN

#define UART_UART_9BITADDR_9BITEN   (1 << 15)    /* Enable 9-bit mode. */

UART_UART_9BITADDR_ADDR_MASK

#define UART_UART_9BITADDR_ADDR_MASK   (0xFF << 0)    /* Self-address for 9-bit mode. */

UART_UART_PP_NB

#define UART_UART_PP_NB   (1 << 1)    /* 9-bit support */

UART_UART_PP_SC

#define UART_UART_PP_SC   (1 << 0)

Enumeration Types

uart_fifo_rx_trigger_level

enum uart_fifo_rx_trigger_level
UART RX FIFO interrupt trigger levels.

The levels indicate how full the FIFO should be before an interrupt is generated. UART_FIFO_RX_TRIG_3_4 means that an interrupt is triggered when the FIFO is 3/4 full. As the FIFO is 8 elements deep, 1/8 is equal to being triggered by a single character.

Enumerator
UART_FIFO_RX_TRIG_1_8
UART_FIFO_RX_TRIG_1_4
UART_FIFO_RX_TRIG_1_2
UART_FIFO_RX_TRIG_3_4
UART_FIFO_RX_TRIG_7_8

uart_fifo_tx_trigger_level

enum uart_fifo_tx_trigger_level
UART TX FIFO interrupt trigger levels.

The levels indicate how empty the FIFO should be before an interrupt is generated. Note that this indicates the emptiness of the FIFO and not the fullness. This is somewhat confusing, but it follows the wording of the LM4F120H5QR datasheet.

UART_FIFO_TX_TRIG_3_4 means that an interrupt is triggered when the FIFO is 3/4 empty. As the FIFO is 8 elements deep, 7/8 is equal to being triggered by a single character.

Enumerator
UART_FIFO_TX_TRIG_7_8
UART_FIFO_TX_TRIG_3_4
UART_FIFO_TX_TRIG_1_2
UART_FIFO_TX_TRIG_1_4
UART_FIFO_TX_TRIG_1_8

uart_flowctl

enum uart_flowctl

Enumerator
UART_FLOWCTL_NONE
UART_FLOWCTL_RTS
UART_FLOWCTL_CTS
UART_FLOWCTL_RTS_CTS

uart_interrupt_flag

enum uart_interrupt_flag
UART interrupt masks.

These masks can be OR'ed together to specify more than one interrupt. For example, (UART_INT_TXIM | UART_INT_TXIM) specifies both Rx and Tx Interrupt.

Enumerator
UART_INT_LME5
UART_INT_LME1
UART_INT_LMSB
UART_INT_9BIT
UART_INT_OE
UART_INT_BE
UART_INT_PE
UART_INT_FE
UART_INT_RT
UART_INT_TX
UART_INT_RX
UART_INT_DSR
UART_INT_DCD
UART_INT_CTS
UART_INT_RI

uart_parity

enum uart_parity

Enumerator
UART_PARITY_NONE
UART_PARITY_ODD
UART_PARITY_EVEN
UART_PARITY_STICK_0
UART_PARITY_STICK_1