TM4C123 Timer Trigger ADC conversion

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Timer Trigger ADC conversion

For digital signal processing, not only the precision of the ADC conversion result is important, the precision of the time that the analog input is sampled is also important. Using software trigger conversion does not yield precision timing especially when there are other software tasks running at the same time. One way of getting precision sampling timing interval is to use the timer to trigger the conversion. To do so:

  1. Configure the ADC to use timer trigger
    The four bits of ADCEMUX register for the sample sequencer used should be loaded with the value of 5 for timer trigger.
  2. Configure a timer to generate periodic timeout
    The periodic timer function is covered here.
  3. Connect timer to ADC trigger.
    To connect the timer to ADC trigger, the TAOTE or TBOTE bit of the GPTMCTL should be set to 1.

The most accurate sampling method is timer-triggered sampling (EM3=0x5). On the TM4C123, the MUX fields are 4 bits wide, allowing us to specify channels 0 to 11. The following are the steps to configure the ADC to sample a single channel at a periodic rate:

  1. Enable the ADC clock in the SYSCTL_RCGCADC_R register.
  2. Bits 3 – 0 of the ADC0_PC_R register specify the maximum sampling rate of the ADC. Set the maximum sampling rate at 125 kHz. This will require less power and produce a longer sampling time, creating a more accurate conversion.
  3. Set the priority of each of the four sequencers. Use just one sequencer, so the priorities are irrelevant, except for the fact that no two sequencers should have the same priority. The default configuration has Sample Sequencer 0 with the highest priority, and Sample Sequencer 3 as the lowest priority.
  4. Configure the timer to run at the desired sampling frequency. Enable the Timer0 clock by setting bit 0 of the SYSCTL_RCGCTIMER_R register. First set bit 5 of the TIMER0_CTL_R register to activate TAOTE, which is the Timer A output trigger enable. Secondly, do not arm any Timer0 interrupts. The rate at which the timer rolls over determines the sampling frequency. Let prescale be the value loaded into TIMER0_TAPR_R, and let period be the value loaded into TIMER0_TAILR_R. If the period of the bus clock frequency is t, then the ADC sampling period will be t *(prescale + 1)*(period + 1). The fastest sampling rate is determined by the speed of the processor handling the ADC interrupts and by the speed of the main program consuming the data from the FIFO. If the bus clock is 80 MHz, the slowest possible sampling rate for this example is 80MHz/232, which is about 0.018 Hz, which is every 55.56 seconds.
  5. Before configuring the sequencer, we need to disable it. To disable sequencer 3, we write a 0 to bit 3 (ASEN3) in the ADC0_ACTSS_R register. Disabling the sequencer during programming prevents erroneous execution if a trigger event were to occur during the configuration process.
  6. Configure the trigger event for the sample sequencer in the ADC0_EMUX_R register. For this example, we write a 0101 to bits 15–12 (EM3) specifying timer trigger mode for sequencer 3.
  7. For each sample in the sample sequence, configure the corresponding input source in the ADC0_SSMUXn register. In this example, we write the channel number (0, 1, 2, or 3) to bits 3–0 in the ADC0_SSMUX3_R register.
  8. For each sample in the sample sequence, Configure the sample control bits in the corresponding nibble in the ADC0_SSCTLn register. When programming the last nibble, ensure that the END bit is set. Failure to set the END bit causes unpredictable behavior. Sequencer 3 has only one sample, so we write a 0110 to the ADC0_SSCTL3_R register. Bit 3 is the TS0 bit, which we clear because we are not measuring temperature. Bit 2 is the IE0 bit, which we set because we want to request an interrupt when the sample is complete. Bit 1 is the END0 bit, which is set because this is the last (and only) sample in the sequence. Bit 0 is the D0 bit, which we clear because we do not wish to use differential mode.
  9. If interrupts are to be used, write a 1 to the corresponding mask bit in the ADC0_IM_R register. We want an interrupt to occur when the conversion is complete (set bit 3, MASK3).
  10. We enable the sample sequencer logic by writing a 1 to the corresponding ASENn. To enable sequencer 3, we write a 1 to bit 3 (ASEN3) in the ADC0_ACTSS_R register.
  11. The priority of the ADC0 sequencer 3 interrupts are in bits 13–15 of the NVIC_PRI4_R register.
  12. Since we are requesting interrupts, we need to enable interrupts in the NVIC. ADC sequencer 3 interrupts are enabled by setting bit 17 in the NVIC_EN0_R register.
  13. Lastly, we must enable interrupts in the PRIMASK register.

The timer starts the conversion at a regular rate. Bit 3 (INR3) in the ADC0_RIS_R register will be set when the conversion is done. This bit is armed and enabled for interrupting, so conversion complete will trigger an interrupt. The IN3 bit in the ADC0_ISC_R register triggers the interrupt. The ISR acknowledges the interrupt by writing a 1 to bit 3 (IN3). The 12-bit result is read from the ADC0_SSFIFO3_R register.